Predictable multi-core architecture

This area of our research is concerned with the development of System-on-a-Chip (SoC) architecture as the foundation for the component-based design of embedded applications. At the core of this SoC architecture is a time-triggered network-on-a-chip for the predictable interconnection of heterogeneous tiles, possibly IP cores. An IP core can be a self-contained computer, including system and application software or a custom hardware unit. By providing a single uniform interface to all types of IP cores for the exchange of messages, the architecture supports the component-based design of large applications and enables the massive reuse of IP cores. The time-triggered network-on-a-chip offers inherent fault isolation to facilitate the seamless integration of independently developed IP cores, possibly with different criticality levels. Furthermore, we develop gateways for accessing chip-external networks with selective redirection of information, fault containment and external clock synchronization.

Research activities in this focus area include:

  • Avoidance and bounding of temporal interference for different resource types of multi-core chips

  • Time-triggered Networks-on-a-Chip (NoC) with inherent fault isolation and temporal predictability

  • On-chip fault tolerance mechanisms (e.g., fault recovery, active redundancy)